The present invention relates to a semiconductor component having a pn junction present in a semiconductor layer and a passivation layer applied to a surface of the semiconductor layer.
In order to achieve a sufficiently high blocking capability of power semiconductor components, for example made of Si or SiC, suitable measures for controlling the high electric field strengths have to be implemented particularly in those regions in which a pn junction comes to the surface. In these regions in which semiconductor junctions come to the surface—usually in the edge region of the component—in the absence of additional measures, in the event of the semiconductor junction being reverse-biased, an avalanche generation may commence still distinctly before the dielectric strength in the bulk, that is to say within the semiconductor body, is reached. In this case, the lower dielectric strength in the edge region reduces the dielectric strength of the entire component. The required dielectric strength of customary power components, for example of IGBTs, lies between 600 V and 6.5 kV, by way of example.
The problem of the prematurely commencing edge breakdown may additionally be aggravated by the action of surface charges in a passivation layer that is usually applied to the edge region for the purpose of increasing the breakdown strength.
In order to increase the dielectric strength in the edge region, or in order to avoid an excessively great reduction of the dielectric strength at the edge in comparison with the bulk, a wide variety of concepts are known which aim to reduce the electric field that forms at a blocking pn junction at the surface and to keep the potential conditions stable over the long term.
In this case, it is possible, in principle, to distinguish conceptionally between the so-called mesa edge termination and the planar edge termination. In the case of the first concept, the semiconductor edge is contoured in the form of ground bevels or trenches through the blocking pn junctions, as is described for example in Baliga: “Power Semiconductor Devices”, PWS Publishing, 1995, page 116. In the case of the second concept, suitable mask techniques are used to set either the lateral course of the diffusion profile and/or the reduction of the field strength in external space by means of insulating or semi-insulating layers, if appropriate in combination with field plates.
An overview of various embodiments of mesa edge terminations may be found for example in Gerlach: “Thyristoren” [“Thyristors”], Halbleiter-Elektronik, [Semiconductor Electronics], vol. 12, Springer-Verlag, 1979, page 151 et seq.
The planar edge termination is widespread in IC technology or in modern semiconductor switches, such as IGBTs or power MOSFETs, and also the associated freewheeling diodes. Some of the most important embodiments of such planar edge terminations are described briefly below.
Components with planar edge terminations contain a pn junction in the component which comes to the surface at a distance from an edge of the component. In order to produce such a pn junction, by way of example, a contiguous, highly doped region is introduced into a more weakly doped semiconductor layer, as is described as a result for example in Baliga, loc. cit., page 82. Due to the well-type course of the semiconductor junction, the electric field lines are crowded together to a greater extent in the region of greatest curvature and the avalanche generation commences prematurely here. In this case, this effect is all the more pronounced, the higher the curvature and the lower the basic doping of the semiconductor layer, or the shallower the introduced well.
In order to counteract that, by way of example, additional, floating field limiting rings are incorporated, which act as voltage dividers and therefore reduce the curvature of the potential lines in the edge region, this being described in Baliga, loc. cit., pages 98–100. Said field rings are doped complementarily with respect to the basic doping.
A further known possibility for attenuating field spikes that occur at the pn junction consists in smoothing the potential distribution by means of an equipotential area above the pn junction in the form of an electrically conductive, in particular metallic, field plate. The metal electrode is kept at an appropriate distance from the semiconductor surface by means of an insulating intermediate layer, generally a semiconductor oxide. Such a field plate structure, which can also be combined with a field ring structure, is described for example in Baliga, loc. cit., pages 100–102, or in EP 0 341 453 A1.
A further known edge termination functioning according to the so-called RESURF principle (RESURF=Reduced Surface Field) is illustrated in FIG. 1. Such an edge termination is described for example in J. A. Appels et al., Philips Research Report 35 (1980), pages 1–13.
FIG. 1 shows a semiconductor body 100 having a semiconductor layer 12, which has an n-type basic doping in the example. In the region of a side 101 of the semiconductor body, a highly doped well 20, of a complementary power type with respect to the semiconductor layer 12, is introduced into said semiconductor layer 100 for the purpose of forming a pn junction, said well being p-doped in the example and ending at a distance from an edge 102 of the semiconductor body 100. A field expansion at the surface 101 of the semiconductor body 100 is achieved by means of a more weakly doped p-type region 30, which is also designated as π region. It extends in the so-called edge region of the semiconductor body 100 between the more highly doped well 20, which forms the anode in a diode, and a channel stopper 40 that is arranged at the edge 102 and is of the same power type as the basic doping but doped more highly. The π region 30 may be formed such that it is shallower or deeper than the anode 20 in the vertical direction of the semiconductor body, it being possible for said anode also to be completely embedded in the π zone 30 in a manner that is not specifically illustrated.
This concept and edge concepts additionally explained below can be applied to any desired semiconductor components having a pn junction, the component in FIG. 1 being illustrated as a diode for the sake of simplicity, the anode zone of which diode is formed by the p-doped well 20. The cathode zone is formed by a more heavily doped semiconductor zone 14 adjoining the semiconductor layer 12 in the region of a rear side 103 of the semiconductor body 100. The reference symbols 52 and 54 designate terminal electrodes.
The JTE structure (JTE=Junction Termination Extension) that is illustrated in FIG. 2 and is described for example in Temple, V. A. K., IEEE Electronic Devices 39, (1983), pages 954–957, constitutes a modification of the RESURF structure. In the case of the JTE structure, a more weakly p-doped π zone 32 is pulled back from the channel stopper 40 in the direction of the anode 20, it being possible for the π zone to be connected annularly to the p-doped well, as is illustrated by a broken line, or else to contain this completely, as is illustrated by the solid line. The mode of operation of the JTE structure corresponds to that of the RESURF structure.
FIG. 3 shows a further known edge termination having a so-called VLD structure (VLD=Variation of Lateral Doping). Such an edge termination structure, which is described for example in EP 0168771 A1, has a π zone 34 that is doped more weakly than the well 20 and whose doping decreases in the lateral direction of the semiconductor body 100 in the direction of the edge 102. In this case, the doping of the π zone 34 may merge continuously or discontinuously with the doping of the heavily doped well 20.
In order to limit the space charge zone at the outermost semiconductor edge in the case of a reverse-biased pn junction, a channel stopper (reference symbol 40 in the figures) may be provided in the case of all the edge terminations explained.
Furthermore, variants and combinations of the edge terminations explained are already being used. Thus, by way of example, the JTE structure with an additional field plate construction proves to be expedient. The choice of the respective edge termination also depends not least on what thermal budget can be made available for the indiffusion of dopant atoms into the semiconductor layer.
Apart from the field plate structure, which already shields the semiconductor junction well from external space by means of the at least one metal electrode, the requirement for a reliable surface passivation of the semiconductor layer is also increasingly being manifested in the case of the other edge terminations explained. This is because surface charges at the surface of the semiconductor body likewise influence the potential distribution.
Such a passivation layer at the surface 101 of the semiconductor body above the pn junction is designated by the reference symbol 60 in FIGS. 1 to 3.
It has been the view previously that the passivation layer ought to be free of stationary charges and also of mobile charges that may drift in the electric field of the reverse-biased semiconductor junction and thus form the cause of blocking instabilities.
Moreover, passivation layers must be sufficiently electrically robust to withstand the peak field strengths at the surface, which, depending on the structure, may far exceed the value of the bulk breakdown field strength, which is approximately 200 kV/cm in the case of silicon. Dielectrics such as thermal oxides, Si3N4 layers, silicones or organic materials such as polyimide, for example, are generally used as such passivation layers.
In addition to such dielectrics, semi-insulating layers such as, for example, amorphous silicon or amorphous carbon are also used as passivation layers for semiconductor components, which are able, on account of their finite specific conductivity, to influence the potential conditions in the semiconductor body with the pn junction. A semiconductor component having such a semi-insulating layer as passivation layer is described in EP 0 077 481 A2, for example. The component described therein comprises an amorphous Si layer on an oxide, which layer serves as a resistive voltage divider between an anodal field plate and a field plate on the channel stopper side. Further components having semi-insulating layers as passivation layers are described in DE-A-27 30 367 or EP 0 400 178 A1, for example.
EP 0 400 178 A1 in this case describes setting, by way of the deposition conditions of the amorphous passivation layer, the electrical conductivity of said layer and the barrier height at the interface between passivation layer and crystalline semiconductor in such a way that an influencing of the potential conditions at the surface of the blocking component is avoided in the case of the layers described therein comprising amorphous silicon, amorphous hydrogen-containing carbon (aC:H) or amorphous silicon carbide (SiC). This means that: the passivation layer, in the event of the interaction with the electric field of the reverse-biased pn junction at the amorphous-crystalline interface, is permitted to lead only to a band bending with a magnitude such that an inversion or avalanche generation does not occur. This ensures that the semi-insulating passivation layer behaves neutrally and the potential conditions are determined exclusively by the predetermined edge structure. In this case, on account of the good electrical coupling to the substrate, the amorphous layer assumes the potential profile of the reverse-biased component.
On account of the shielding effect of such an amorphous passivation layer, which can be described in a manner analogous to that in the case of a metallic field plate, by its high electronic state density in the mobility gap, a good stability of the component passivated in this way is achieved.
EP 0 624 901 A1 describes a semiconductor component having a passivation layer comprising an amorphous hydrogen-containing carbon, said layer having a boron doping of between 0.1% and 4% in order to avoid an inversion layer.
Such amorphous passivation layers are obtained in a PECVD process (PECVD=Plasma Enhanced Chemical Vapor Deposition), which, by way of the deposition conditions, permits the physical properties of the passivation layers, in particular the resistivity thereof and the junction resistance thereof with respect to the semiconductor body, to be set within wide limits. The production method and the application of such passivation layers for semiconductor components are described in detail in EP 0 381 111 A2, for example.
The edge termination concepts explained have their area of use depending on technology, but are subject more or less to the following disadvantages that drastically increase as the blocking capability of the components increases:    1. The production outlay for the edge termination increases with higher reverse voltage and constrains a high process complexity.    2. The optimization of the field profile is not possible simultaneously for the static and dynamic blocking case. This leads to impairment of the turn-off robustness particularly in the case of rapidly switching power components. If the semiconductor layer with the semiconductor junction is depleted during the transition from the conducting to the blocking state, then a reverse current flows that has a considerable influence on the potential conditions in the edge region during the rise in the reverse voltage.    3. As the required dielectric strength of the components increases, the induction effect of surface charges becomes ever greater when the semiconductor has a low basic doping. The susceptibility to blocking instabilities increases. The demand for a long-term reliability makes ever more stringent requirements of the passivation layers.    4. As the required dielectric strength increases, more and more space has to be made available for the edge termination in order to control the surface field strength. In high-voltage components, the width of said edge may finally amount to more than triple the thickness of the base (reference symbol 12 in FIGS. 1 to 3) and, in the case of small chips, leads to a considerable loss of active area.